Multiprocessor (MP) systems are computing systems comprised of a few or up to hundreds or thousands of processing elements (PEs). While the power of a multiple-instruction multiple-data (MIMD) MP computer system lies in its ability to execute independent threads of code simultaneously, the inherently asynchronous states of the PEs (with respect to each other) makes it difficult in such a system to enforce a deterministic order of events when necessary. Program sequences involving interaction between multiple PEs such as coordinated communication, sequential access to shared resources, controlled transitions between parallel regions, etc., may require synchronization (such as barrier and/or eureka synchronization) of the PEs in order to assure proper execution. One such invention having routers, networks, and synchronization apparatus and methods is described further in copending U.S. Pat. No. 6,085,303, issued Jul. 4, 2000, entitled “SERIALIZED, RACE-FREE VIRTUAL BARRIER NETWORK”.
Some MP systems having symmetric distributed multiprocessors use a coherent model of cache. One such system is described in application Ser. No. 08/971,184 filed Nov. 17, 1997 entitled “MULTI-DIMENSIONAL CACHE COHERENCE DIRECTORY STRUCTURE”.
There is a need in the art for an improved node controller apparatus and method to improve communications between various portions of an MP system. Further, there is a need for a node controller that will “scale well” providing excellent performance-cost benefits for both small and large systems. Further, there is a need for a node controller that has very high flexibility, performance and speed.